1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a BiCMOS transistor which enhances reliability of a device by improving the high frequency characteristics of a bipolar transistor.
2. Description of the Related Art
A bipolar transistor of high performance used for cellular phones or wireless LAN or the like, which has recently become popular, can reduce the gate delay time, but limits the number of transistors that can be integrated on a single chip because of the large quantity of emission heat. On the other hand, a Complementary MOS (hereinafter, referred to as CMOS) circuit is very advantageous from a power consumption viewpoint in that it can minimize the quantity of heat generated from the circuit. However, the current driving ability of a CMOS transistor is not enough to charge and discharge a capacitive load, so it has a limitation on the operating speed. Thus, in case of a digital circuit that requires a high-speed operation or is combined with an analog circuit, it is advantageous to use a BiCMOS structure having a combination of CMOS and bipolar transistors.
FIGS. 1a to 1d are sectional views approximately showing a conventional BiCMOS fabrication process, which refers to xe2x80x9cProcess Integration Technology for sub-30 ps ECL BiCMOS using Heavily Boron Doped Epitaxial Contact (HYDEC)xe2x80x9d published in IEDM94-441 by Y. Kinishita, et al. In the drawings, the left side represents a transistor region and the right side represents a MOS transistor region, respectively.
Referring to FIG. 1a, a gate oxide film 6 is formed by forming an oxide film with a predetermined thickness on a semiconductor substrate 2 that is divided into an active region and a non-active region by a field oxide film 4. An undoped polysilicon film 8 is deposited on the gate oxide film 6, and then a nitride film 10 is deposited on the entire surface. Next, the nitride film 10, undoped polysilicon film 8 and gate oxide film 6 of the bipolar transistor region is sequentially patterned by a photo etching process and then the exposed gate insulating film is removed by wet etching. At this time, as shown therein, an undercut is formed below the undoped polysilicon film 8 of the bipolar transistor region. Thereafter, the polysilicon film 8 formed on the MOS transistor region becomes a gate electrode and the polysilicon film 8 formed on the bipolar transistor region becomes an external base.
Referring to FIG. 1b, a polysilicon film 12 doped with boron (B) at high concentration is deposited on the entire surface of the semiconductor substrate, and then etch-back is performed on this polysilicon film. Since the polysilicon film 12 doped with boron (B) at high concentration is favorable in step coverage, it is easily deposited even on the undercut region formed on the sides of the gate oxide film, which is relatively thin as shown therein, and thus the undercut is buried with the doped polysilicon film.
Referring to FIG. 1c, the polysilicon film doped with boron (B) at high concentration is anisotropicly etched. Then, as shown, the polysilicon film 12 doped with boron (B) at high concentration remains on the undercut region formed on the bipolar transistor. Continually, an oxide film is deposited on the entire surface of the semiconductor substrate at a predetermined thickness and then etched back to form a spacer 14 for short-circuiting the external base and emitter of the bipolar transistor. Next, a base 16 is formed by implanting impurities into the exposed semiconductor substrate 2 in the bipolar transistor region. Subsequently, the doped polysilicon film and the oxide film are deposited along the entire surface of the resultant material and then sequentially patterned to form an emitter 18 and capping layer 20 of the bipolar transistor.
Referring to FIG. 1d, the undoped polysilicon film is patterned by the photo etching process to form a gate electrode 8b of the MOS transistor and an external base 8a of the bipolar transistor. Next, a spacer 22a and 22b is formed on the sides of the external base 8a and gate electrode 8b by depositing an oxide film on the entire surface of the semiconductor substrate and then conducting anisotropic etching. Next, using this spacer as a mask, ions of high concentration are implanted into the semiconductor substrate and then heat treatment is carried out. Then, the external base 8a of the bipolar transistor and the gate electrode 8b of the MOS transistor each are doped at high concentration. In addition, a high concentration impurity region 24 is formed in the bipolar transistor region and a source/drain 26 is formed in the MOS transistor region.
As stated above, according to the prior art process, the high concentration impurity region 24 is formed in the bipolar transistor region by the post heating process, and this increases the parasitic capacitance between the base and the collector, thereby degrading the high frequency characteristics of the bipolar transistor. In addition, the external base and the internal base existing in a channel are connected to each other with a small area as shown in FIG. 1b, and this increases the overall base resistance Rb, thereby reducing the high frequency characteristics.
The present invention is designed in consideration of the problems of the prior art, and therefore it is an object of the present invention to provide a method for fabricating a BiCMOS transistor which reduces base resistance and parasitic capacitance between the base and collector, improving the high frequency characteristics of a bipolar transistor and enhanceing performance of the device.
To achieve the above object, there is provided a method for fabricating a BiCMOS transistor in accordance with the present invention, comprising the steps of: forming a field oxide film for device isolation and a buried oxide film on a semiconductor substrate; forming a well where a MOS transistor is to be formed and a collector of a bipolar transistor on the semiconductor substrate; forming a gate insulating film on the semiconductor substrate; forming a gate electrode of the MOS transistor and an external base of the bipolar transistor on the gate insulating film; forming a nitride film for a spacer on the resultant material; removing the nitride film for the spacer within the bipolar transistor region; selectively forming a silicon layer and a polysilicon layer in the bipolar transistor region; forming an insulating film on the polysilicon layer; forming a spacer on the sides of the gate electrode of the MOS transistor and on the sides of the external base of the bipolar transistor; and forming a source/drain of the MOS transistor.
In the present invention, the step of selectively forming a silicon layer and a polysilicon layer is carried out by a selective epitaxial growth method. And, when the selective epitaxial growth process is carried out, high concentration impurities are added.
In addition, in the step of removing the nitride film for the spacer in the bipolar transistor region, it is preferable that the gate insulating film formed below the external base is also completely removed.